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128Kx8 LP SRAM EM6128K800V Series GENERAL DESCRIPTION
The EM6128K800V is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The EM6128K800V is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The EM6128K800V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible
FEATURES
Fast access time: 35/55/70ns Low power consumption: Operating current: 12/10/7mA (TYP.) Standby current: -L/-LL version 20/1A (TYP.) Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage: 1.5V (MIN.) Package: 32-pin 450 mil SOP 32-pin 600 mil P-DIP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 36-ball 6mm x 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
Vcc Vss A0-A16 DECODER
128Kx8 MEMORY ARRAY
DQ0-DQ7
I/O DATA CURCUIT
COLUMN I/O
CE# WE# OE# CE2
CONTROL CIRCUIT
PIN DESCRIPTION
SYMBOL A0 - A16 DQ0 - DQ7 CE#, CE2 WE# OE# Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Enable Input Write Enable Input Output Enable Input Power Supply Ground
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128Kx8 LP SRAM EM6128K800V Series PIN CONFIGURATION
SOP/P-DIP
A4 A3 A2 A1 A0 CE# DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 TSOP-I/STSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A5 A6 A7 OE# UB# LB# DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8
A11 A9 A8 A13 WE# CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
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128Kx8 LP SRAM EM6128K800V Series
TFBGA A B C D E F G H A0 DQ4 DQ5 Vss Vcc DQ6 DQ7 A9 1 A1 A2 CE2 WE# NC A3 A4 A5 A6 A7 A8 DQ0 DQ1 Vcc Vss DQ2 DQ3 A14 6
OE# A10 2
NC CE# A11 3
NC A16 A12 4
A15 A13 5
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128Kx8 LP SRAM EM6128K800V Series ABSOLUTE MAXIMUN RATINGS*
PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT TSOLDER RATING -0.5 to 4.6 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 260 C W mA C C UNIT V
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read Write CE# H L L L OE# X H L X WE# X H H L I/O OPERATION High-Z High-Z DOUT DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Operating Power supply Current SYMBOL Vcc VIH*1 VIL*2 ILI ILO VOH VOL ICC ICC1 Standby Power Supply Current ISB ISB1 TEST CONDITION MIN. 2.7 2.0 -0.2 -1 -1 2.2 -35 -55 -70 TYP. *5 3.0 2.7 12 10 7 1 0.3 20 1 MAX. 3.6 Vcc+ 0.3 0.6 +1 1 0.4 35 30 25 5 0.5 80 10 UNIT V V V A A V V mA mA mA mA mA A A
Vcc VIN Vss VCC VOUT VSS, Output Disabled IOH = -1mA IOL = 2mA Cycle time = Min. CE# = VIL , II/O = 0mA
Cycle time = 1s CE#0.2V and II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH CE# V VCC - 0.2V -L -LL
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. 10A for special request 5. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25C
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128Kx8 LP SRAM EM6128K800V Series CAPACITANCE (TA = 25C , f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX. 6 8
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH MIN. 35 10 5 10 -35 MAX. 35 35 25 15 15 -55 MAX. 55 55 30 20 20 70 MAX. 70 70 35 25 25 UNIT ns ns ns ns ns ns ns ns ns
MIN. 55 10 5 10
MIN. 70 10 5 10
SYM. tWC tAW tCW tAS tWP twr tDW tDH tOW* tWHZ* MIN. 35 30 30 0 25 0 20 0 5 -
-35 MAX. 15
MIN. 55 50 50 0 45 0 25 0 5 -
-55 MAX. 20
MIN. 70 60 60 0 55 0 30 0 5 -
70 MAX. 25
UNIT ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
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128Kx8 LP SRAM EM6128K800V Series TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA tOH
Dout
Previous Data Valid
Data Valid
READ CYCLE 2 (CE#, CE2 and OE# controlled) (1,3,4,5)
tRC Address
tAA CE#
OE#
tACE tOH tOE tOLZ tCLZ tOHZ tCHZ Valid Data
Dout
High-Z
CE2
Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
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128Kx8 LP SRAM EM6128K800V Series
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address CE# tAW
tCW CE2 WE# tAS tWP tWR
tWHZ High-Z Dout (4) tDW High-Z Din WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address CE# tAS tCW CE2 WE# tWP tAW Valid Data
tOW (4) tDH
tWR
tWHZ Dout tDW High-Z Din Valid Data tDH High-Z
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128Kx8 LP SRAM EM6128K800V Series
Notes : 1. WE#, CE# must be high during all address transitions. 2. A write occurs during the overlap of a low CE#, low WE#. 3. During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6. tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
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128Kx8 LP SRAM EM6128K800V Series DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL VDR IDR TEST CONDITION CE# V VCC - 0.2V VCC = 1.5V CE# V VCC - 0.2V See Data Retention Waveforms (below) -L -LL -LLE -LLI MIN. 1.5 0 tRC* TYP. 1 0.5 0.5 MAX. 3.6 50 5 10 UNIT V A A A ns ns
tCDR tR
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR 1.5V
Vcc
Vcc(min.) tCDR CE# Vcc-0.2V
Vcc(min.)
tR
VIH
CE#
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR 1.5V
Vcc
Vcc(min.) tCDR CE2 0.2V
Vcc(min.)
tR
VIH
CE2
VIH
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128Kx8 LP SRAM EM6128K800V Series PACKAGE OUTLINE DIMENSION
32 pin 450 mil SOP Package Outline Dimension
32 pin 600 mil P-DIP Package Outline Dimension
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128Kx8 LP SRAM EM6128K800V Series
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
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128Kx8 LP SRAM EM6128K800V Series
36-ball 6mm x 8mm TFBGA Package Outline Dimension
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128Kx8 LP SRAM EM6128K800V Series
Product ID Information
EM
61
28K
8
0
0
V
B
A
- 35
IF*
Configuration: Option 8: x8 Voltage: 16: x16 V: 3V W: 2.7V Address Density ~5.5V 28K: 128K EOREX T: 5V Package: Manufactured S: STSOP Memory P: PDIP F: SOP B: TFBGA T: TSOP I: TSOP-I
* Product ID example
SRAM Family 61: Standard
Version Option Speed: 35ns 55ns 70ns TEMP: Blank: Normal I: Industrial Pb-Free PKG: Blank: Normal F: Pb-free
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128Kx8 LP SRAM EM6128K800V Series
(c)COPYRIGHT 2004 EOREX CORPORATION
The information in this document is subject to change without notice.
Printed in Canada
EOREX makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of EOREX. EOREX subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications.
EOREX CORPORATION http://www.eorex.com sales@eorex.com 2F., No. 301-3, Guang-Ming 6th Rd., Chu-Pei City, Hsinchu County, Taiwan 302, ROC TEL: +886-3-5585138 FAX: +886-3-5585139
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